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PoE Problem to Ponder –
The Return

by Peter Vaughan
Peter Vaughan
  Manager of Product Applications
Power Integrations

Test your knowledge of designing printed circuit board layouts for power supplies by answering the three questions below. Then check your answers and register for a chance to win an Apple iPod Nano!


The circuit below shows a three output VoIP telephone power supply using a DPA-Switch power conversion IC. The low-cost discrete PoE interface circuit identifies the supply as Class 3 per IEEE802.3af. Class 3 limits the maximum power drawn from the network cable to 12.95 W.

 


As new features are added to PoE powered products, for example a color display or camera to a VoIP phone, the power requirements often rise. Why is it desirable to increase efficiency in the PoE power supply as load requirements rise?
 
See the answer to Question 1.

With a fixed input power limit, increases in efficiency directly increase the amount of power that can be delivered to the output. For example at 75% efficiency the available output power is 9.7 W but at 85% efficiency that rises to 11 W.

           Close this answer window.

 

Part 1

Synchronous rectification is employed to boost the efficiency of the output stage.  For a single output 3.3 V, 3 A forward converter what would you estimate the increase in output power to be by changing from diode rectification to synchronous rectification (Q21, Q22) as shown in Figure 1?  Assume the following:

  1. Converter operating on duty cycle of 50%
  2. Schottky diode VF of 0.4 V
  3. MOSFET RDS(ON) of 30 mW and operating duty cycle of 50%.

Part 2

The DPA-Switch (U1) used in this design has a programmable current limit.  By changing the value of R2 the current limit can be programmed from 100% to 30% of the internal maximum.  What single component change does this feature allow the designer to make for higher efficiency without changing anything else in the design?  Is there a limit to this approach?

See the answer to Question 2.

Part 1

1. Diode Rectification Case

The average current in the output diodes is equal to the output current multiplied by the duty cycle.

Answer 2, Image 1

2. Schottky Rectification Case

As the voltage drops across the MOSFETs are not constant we need to calculate the RMS current through both devices.

Answer 2, Image 2

Answer 2, Image 3

So we see that the 50% duty cycle will result in identical dissipation in both MOSFETs (for identical MOSFETs).

Answer 2, Image 4

Total dissipation in the MOSFETs is 0.269 W.

3. Increase in Output Power

Increase in output power is the difference in losses between the two rectification schemes:

1.2 W – 0.269 W = 0.93 W

In practice the real world improvement is somewhat lower than this.  For example the MOSFET drive losses have been excluded and with passive drive the freewheeling MOSFET is only driven for part of the off time (up until the transformer is reset).

Part 2

The programmable current limit allows the selection of a larger DPA-Switch device with a lower RDS(ON) MOSFET.  The lower RDS(ON) lowers conduction losses and improves efficiency.  The programmable current limit allows the current limit of the larger device to be programmed to be the same as the original, smaller device.  This avoids the need to change the transformer or the rest of the circuit to operate at a higher peak primary current.

There is a limit to this approach because as a larger device is selected for lower RDS(ON), the MOSFET capacitances also increase, causing an increase in switching losses.  Therefore for a given design, operating frequency and input voltage there is an optimum device size that minimizes switching and conduction losses.  Typically this is one device size larger (half the value of RDS(ON)).

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Again, referring to Figure 1, w hat is the role of C21 when connected in series with Q21 in the synchronous rectification circuit?

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See the answer to Question 3.

  1. Capacitor C21 is added to prevent an abnormal condition that occurs during brown out or power down.

    Answer 3, Image 1

    If C21 is omitted during normal operation the converter will operate normally, the positive voltage that appears across the secondary winding during the on-time of the primary switch will turn on Q21.

    However once the primary stops switching the current through L2 will ramp to zero delivering energy into the output capacitors.  If the output capacitors are close to the output voltage then at the point the L2 current falls to zero a positive voltage appears at the gate of Q21, turning it on and allowing the current to ramp in the opposite directly through L2.  The current loop formed is from the output capacitors (C22-C24), L2, the secondary winding of T1 and Q21 back to the output capacitors.

    The current ramp eventually causes the transformer core (T1) to saturate at which point the gate drive for Q21 is removed and it starts to turn off.  The energy in L1 and T1 cause an inductive voltage spike to appear at the gate of Q22, turning it on and reducing the gate drive of Q21.

    The magnitude of the voltage spike seen by Q22 is typically much greater than its maximum rating causing device failure.

    By adding C21, when switching stops, the DC voltage that appears at the gate of Q21 when the L2 current reaches zero is blocked, preventing Q21 turning one and therefore preventing the conditions that can damage Q22.

    During normal operation C21 acts as a charge pump, providing sufficient charge to turn on Q21 as the secondary winding voltage swings positive, with the maximum gate voltage clamped by VR21.  As the secondary winding swings negative, C21 is discharged (reset) via VR21, ready to turn on Q21 on the next switching cycle.

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