1. This waveform is characterized by a steady rise of current and this rise continues for the duration of the ON time. This characteristic linear ramp is representative of the Drain current waveform and can be matched to the current flowing through loop 1.
2. This waveform is characterized by a steady fall of current from approximately the end of ON time. This is a characteristic linear ramp down of the secondary diode current and can be matched to the current flowing through loop 4.
3. This waveform has two distinct characteristics – at turn on, a negative current, and at turn off - a positive current spike. The secondary winding voltage has a similar characteristic, negative while the MOSFET is on and positive when the switch is off with the negative voltage being larger than the positive voltage. This cannot be the current through the output diode because the magnitude and duration are too short so it suggests that the current must be flowing through loop 3.
4. This waveform also occurs at the MOSFET turn off transition. At this point the leakage and magnetizing current first charges drain node parasitic capacitances (associated with the MOSFET and transformer). Once the drain voltage exceeds the clamp voltage plus input voltage diode D5 will conduct. As some of the leakage energy has already been reset charging the drain node the actual peak current into the clamp is lower than the peak drain current at turn off. This suggests that it must be flowing through loop 2
5. This DC current is characteristic of the output/load current that flows through loop 5. Capacitor C3 filters the secondary switching current so that only DC currents appear in loop 5.

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First a caveat – These loops have been prioritized with the assumption that the switching device uses a MOSFET with high switching speed (and not a bipolar which typically have lower switching speeds).

There are 4 aspects that decide how critical a loop area is to shrink and thereby minimize radiated noise. These 4 aspects are

1. The absolute magnitude of the switched current
2. The rate of change of the switching current (di/dt)
3. The absolute magnitude of the switching voltage
4. The rate of change of switching voltage (dv/dt)

1. Loop 1
   This loop carries the primary switching current. High di/dt currents will create a voltage drop across the impendence of this loop (including the ESR of the input capacitor) and be a source of differential mode EMI. In addition the drain node itself has a high voltage swing together with a high dv/dt and by minimizing the area of this node, the electrostatic coupling and therefore common mode EMI are reduced. Although the absolute magnitude of currents in this loop are smaller than those in loop 4, typically the di/dt is higher and together with the high dv/dt makes this loop the most critical.
   
2. Loop 4
   This loop carries the highest magnitude of switching currents and thus is one of the most powerful radiating antennas in the power supply, as such this loop area must be kept to a minimum. This loop also impacts the leakage inductance losses and therefore primary clamp losses. By minimizing the loop length the trace leakage inductance that is reflected through the transformer (via the turns ratio squared) to the primary is also minimized. Although loop 1 has been designated as most critical this loop is a very close second. Thankfully however, in most power supplies both these loops can be shrunk independently of one another.
   
3. Loop 2
   This loop connects to the primary side clamp circuit. Fast current transients flow within the loop and this area should be minimized. The clamp often causes high voltage, high frequency ringing. Minimizing the loop reduces the coupling of this noise that appears in both conducted and radiated common mode EMI.
   
4. Loop 3
   The primary objective of this loop is to provide a localized pullout current path for the reverse recovery (snap off) current from the secondary diode. The di/dt in this loop is not as high as in loops 1 2 and 3. Furthermore, the peak currents are usually not comparable to the secondary peak currents. However, this loop can be critical for controlling high frequency radiated EMI and should also have a small loop area.
   
5. Loop 5
   Capacitor C3 filters the secondary switching current so that only low frequency DC current appear in loop 5. Since the switching component of current in this loop is negligible, this loop area is not very critical.

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Figure 4: Improved layout for partial circuit shown in Figure 3.

1. Capacitor C1 can be placed physically closer to the switching MOSFET (U1). This facilitates shorter leads to the connecting components thereby reducing trace inductance.
2. The loop area connecting capacitor C1, transformer T1 and switching MOSFET U1 can be minimized as shown in figure 4 above. This is made possible by using pin 4 of the transformer to connect to the positive DC bus, (positive terminal of C1) rather than pin 1, which was used in the original layout.
3. Capacitor C7, which is the bypass capacitor needs to be placed as close as possible to the integrated controller and MOSFET (U1).
4. Drain connection trace width reduced. This section of the track carries high voltage switching signals (high dv/dt). Such signals can capacitively couple to earth ground and cause common mode EMI. A wide trace (larger surface area) would present higher coupling capacitance to earth ground and generate more common mode EMI. Figure 1 shows reduced copper area between transformer and the Drain node. This is also the reason why the connection from transformer T1 to diodes D6 and D7 should not be connected by excessively wide copper traces.
5. Components D7 and C4 are repositioned and the secondary ground has been moved such that the loop area for both the outputs are now minimal. In general for multi output designs it is a good practice to layout the ground trace in the middle of the transformer. This minimizes loop area and improves radiated EMI performance. If you have more than 2 outputs, prioritize the outputs according to highest currents and position the highest current output to have the smallest loop area.
6. Post filter capacitor C9 has been moved physically closer to the output terminals. This minimizes the inductance to the output terminals and reduces output ripple and noise.
7. Y capacitor connection tracks are thick in Figure 3. This is better for high frequency EMI performance. Thicker tracks provide lesser impedance (resistive as well as inductive) at higher frequencies.

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